The present invention relates to a nonvolatile or volatile semiconductor memory component, having memory cells, logic regions and dummy structures with random access, also having a structure which is differentiated into memory cells and logic regions and has a lower oxide layer arranged on a silicon substrate and an upper oxide layer arranged on the lower oxide layer, each memory cell comprising at least one transistor in the transition region between silicon substrate and lower oxide layer and a capacitor in the transition region between lower oxide layer and upper oxide layer, which capacitor is connected to the transistor via a contact hole, which is filled with metal, in the lower oxide layer and comprises a ferroelectric arranged between two electrodes, the electrode which is connected to the transistor and adjoins the lower oxide layer having a relatively great thickness, and each logic region comprising at least one transistor in the transition region between silicon substrate and lower oxide layer, which transistor is connected to an electrode on the topside of the upper oxide layer via a contact hole, which is filled with metal, in the lower oxide layer and the upper oxide layer.
Semiconductor memory components of this type having a ferroelectric capacitor or a capacitor with a high dielectric constant are known, for example, from U.S. Pat. No. 5,854,104 and EP 0 516 031 A1 and are also known as FRAMs or DRAMs. Examples of suitable materials for the ferroelectric of the capacitor are SBT (SBT stands for SrBi2Ta2O9) and SBTN (SBTN stands for SrBi2 (Ta1xe2x88x92xNbx)2O9) or PZT (PZT stands for Pb(Zr1xe2x88x92xTix)O3).
The subject matter of the invention also relates in particular to DRAMs which operate with BST (BST stands for Ba1xe2x88x92xSrxTiO3) or Ta2O3 as the dielectric. These materials also require Pt or the like as an electrode. Moreover, relatively thick lower electrodes are required in order also to use the side wall, on account of the relatively high integration densities.
Platinum, iridium, iridium dioxide, ruthenium, ruthenium dioxide, palladium, strontium-ruthenium trioxide or combinations thereof are usually employed as the material for the thicker electrode of the capacitor, which electrode is connected to the transistor of the corresponding memory cell.
The thickness of this electrode, also referred to below as the lower electrode, is several hundred nanometers, depending on the capacitance required of the ferroelectric capacitor. The ferroelectric or material with a high dielectric constant which is deposited on the thick electrode also contributes to the overall thickness of the capacitor structure. The counterelectrode is deposited on the outside of the ferroelectric or material of high dielectric constant; this counterelectrode is also referred to below as the upper electrode. The overall result is a capacitor structure which is several hundred nanometers thick.
Since this capacitor structure only exists in the cell array of the semiconductor memory component in question, while similarly thick structures do not occur in the logic region of the semiconductor memory component, there is a considerable difference in topology between the cell arrays and the remaining part of the semiconductor memory component, i.e. the logic regions. This topology makes the metalization of the semiconductor memory component considerably more difficult during the fabrication of this component. Moreover, the etching depths through the intermediate oxide (upper oxide layer) to the upper electrode or to a transistor outside the cell array differ considerably.
In view of this prior art, it is an object of the present invention to provide a semiconductor memory component of the type described in the introduction which has a significantly more uniform topology between the cell arrays and the logic regions and therefore, inter alia, can be metalized with fewer problems.
This object is achieved by the subject matter of claim 1. Advantageous refinements of the invention are given in the subclaims.
Accordingly, according to the invention the difference in topology between the memory cells and the logic regions is substantially compensated for or leveled out by providing dummy structures, the thickness of which corresponds to that of the capacitor structures, in the regions which lie outside the ferroelectric capacitors.
Furthermore, in accordance with an advantageous refinement of the invention, there is provision for the through-contacts in the logic regions which are connected to the transistors provided in these regions to be constructed in a similar way to the thick lower electrode of the capacitors in the cell regions. This means that the contact holes in the upper oxide layer in the logic regions are filled with the same material in the same thickness as the thick capacitor electrodes.
This results, in particular, in a fabrication advantage, since the lower, thick capacitor electrodes, the dummy structures in the logic regions, which consist of the same material as the thick capacitor electrodes, and the contacts in the contact holes of the logic regions can be formed in the same fabrication step. The use of the contact vias in the logic regions also makes the etching depth in the intermediate oxide (upper oxide layer) significantly more uniform.
The overall result is that the difference in topology between the memory cells and the logic regions is according to the invention substantially compensated for, with a difference in thickness in favor of the memory cells existing only to the extent of the thickness of the ferroelectric and the upper electrode of the corresponding capacitor. This difference in thickness is characteristically 200+/xe2x88x92100 nm.
In other words, the particular feature of the invention compared to the prior art is the use of the material for the lower, thicker capacitor electrode both for the dummy structures for level compensation and for the contact vias in the logic regions.